This analysis was presented during the MEMSYS 2015 conference as a result of the paper titled "Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC?" , written in collaboration with experts from Chalmers University and Lawrence Livermore National Laboratory. This paper is a third chapter of the memory wall trilogy following "Hitting the Memory Wall: Implications of the Obvious" (1995) and "Reflections on the memory wall" (2004). Memory wall refers to the fact that memory latency is so large that most of the time processors are waiting for data from memory. "Technological evolutions and revolutions notwithstanding, the memory wall has imposed a fundamental limitation to system performance for over 20 years", stated Petar Radojkovic, Memory systems team lead at BSC.
In the paper, BSC experts have recalled that the memory wall has always been defined in terms of main memory latency, not bandwidth. Higher bandwidth may lower memory latency, provided that the selected applications offer sufficient memory-level parallelism (MLP) and that processors can exploit it. But higher bandwidth cannot guarantee better performance because 3D-stacked DRAMs will not reduce idle-system memory latency. Therefore they will not improve the performance of applications with limited MLP. How well the available bandwidth we can be exploited, ultimately depends on the inherent MLP in our targeted workloads.
Like the initial memory wall paper, this study points out something that most of computer architects 'knew' without really understanding. And in order to fully exploit the potential of 3D-stacked DRAMs, we have to really understand what we can and what we cannot expect from these devices", stated Sally A. McKee, Professor at Computer Science Engineering Department of Chalmers University of Technology.
"Also, Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM) are much more than high- bandwidth memory devices. The logic layers in the HMC and HBM offer possibilities for in-memory processing and sophisticated memory controller functionality. Finding a way to use this innovation to build high-performance systems, however, will take time", concluded Petar Radojkovic.
This paper is the first outcome of the collaboration between BSC and Samsung Electronics Co., Ltd. that started in 2013 in the context of memory technologies which are in line with Samsung's high density memory solution including 3D-TSV technology for HPC systems. On one side, the collaboration focuses on analyzing how production HPC applications exercise the current DRAM memory system and evaluating the frequency and locality of memory errors in exiting DDR3 technologies. On the other side, the collaboration pursues the proposal of new architectures and management algorithms to exploit the upcoming non-volatile STT-MRAM memory technologies in HPC systems.