RISC-V CEO Calista Redmond opened the Global Forum with a keynote. The RISC-V organisation has members all around Europe and is located in Switzerland. RISC-V addresses Instruction Set Architectures (ISA), the core definitions out of which processors are built. The total number of members is 690 members from 50 countries globally. The past year showed a growth of 50 percent in new memberships. Some 22.000 people are actively engaged in RISC-V. Predictions are that by 2025, there will be 62,4 billion RISC-V cores in the world. For each person on the Earth, there will be about 10 cores running RISC-V.
From a high performance computing perspective, the presentation by Jean-Marc Denis from the European Processor Initiative was something to look forward to. He gave an overview of the current status. He started by pointing back to 2015 when the European Commission stated that Europe should be in the top 3 of high performance computing by the end of 2020. Europe will not quite make it but is looking now to 2021. However, this was the vision from which it all started.
The European Processor Initiative is a large project. In fact, it is a framework with several projects. The call for the second project has just gone out. It is a series of projects which together will develop a core processor platform for Europe. By 2023, there should be a European exascale system running on the EPI core. To reach this goal, EPI will start with Arm processors which are already there. The EPI team will continue to develop an accelerator based on RISC-V. There are many companies and organisations involved in this endeavour.
One of the companies is called SiPearl. The European Processor Initiative is developing the IP, the intellectual property right but SiPearl will convert the IP into products. SiPearl is looking for an additional 100 million euro to make this happen. The accelerator will initially be implemented as a test chip, based on RISC-V. It will be installed on the chiplets architecture from the EPI platform. By 2022/23 Jean-Marc Denis expects that the EPI will deliver. There are still some problems that need to be solved. There needs to be a software ecosystem in the data centre in the high end space. To date, this does not exist yet so it needs to be developed. The team hopes the RISC-V ecosystem will be mature enough to use it to this purpose.
Other challenges to overcome are the market development uncertainties. Five years from now is still a very long time to go and it takes a lot of money to develop the products. However, Jean-Marc Denis is quite confident that EPI will manage the challenges in time.
There are also other developments within RISC-V which are of interest to high performance computing and could be part of the ecosystem development. One of these developments is the DR1000C, a 512-bit vector chip, developed by NSITEXE. The chip looks a bit like the one used in Fugaku, which is Arm-based. The company is performing performance benchmarking for matrix multiplication which looks very good. The chip is aimed at artificial intelligence and machine learning but also at high performance computing.
The presentation by Xianyi Zhang addressed the OpenBLAS RISC-V "V" vector extension. There is a vector extension defined for RISC-V and Xianyi Zhang is looking at how to port OpenBLAS to that. BLAS involves the basic algorithms that were designed a few decades ago for basic computations like vector-scalar, matrix-vector, and matrix-matrix computations. You can find them at the basic core of the software. These also have high performance implementations on RISC-V in order to smoothly run all your simulation software. For instance, the matrix-matrix multiplication runs 14 times better than if you do it in the standard way. By the end of this year OpenBLAS on RISC-V will be fully optimized. It will be open sourced.
SemiDynamics is looking at high bandwidth IP cores which were introduced at the RISC-V Global Forum. SemiDynamics is part of the European Processor Initiative. The company introduced two new RISC-V cores, namely the Avispado 220 for in-order processing and the Atrevido 220 for out-of-order processing. They can avoid cache misses. They also have an open vector interface in order to connect to your own open vector implementation.
What exactly is a high bandwidth core? If you have very sparse matrices and only once in a while things are needed from this, you have a nice calculation for the first eight elements. Then you have to wait a very long time if you have a cache miss before you can start over again. SemiDynamics has solved this problem with their core that is wider and can better handle cache misses. The chip can be used for machine learning, recommendation systems, key value stores, but also for high performance computing, and especially for sparse data.
The solution can be used in wider systems, so you do not need to have only the small core developed by SemiDynamics but you can put your own vector unit in it. SemiDynamics does not develop the vector unit. You need to develop your own or you purchase it from another company in order to integrate it in your own system-on-a-chip, using the open vector interface.
The open vector interface is a way to connect vector units with other parts of the system or other parts of the core to efficiently manipulate and transfer data from one location to the other. You can concentrate on developing a very fast and very efficient vector processor while SemiDynamics has the high bandwidth processor to connect to the system.
These were some highlights from the RISC-V Global Forum especially with the focus on high performance computing. The European Processor Initiative is part of the bigger RISC-V ecosystem. There are other companies and organisations also developing parts of the whole high performance computing ecosystem. But we should not forget that a large focus of RISC-V is on artificial intelligence and machine learning as well.