Via pillar is a new technology that aims to reduce via resistance and increase electromigration robustness for enhanced performance. Via pillar is supported in IC Compiler II place and route system, and is enabled for what-if analysis in Design Compiler Graphical. This includes insertion of via pillars in the netlist, modelling of via pillars in virtual route, legalized placement of via pillars, as well as detailed routing, extraction and timing to support via pillars. The multi-source CTS with hybrid clock mesh in IC Compiler II inserts via pillars on clock nets, and then the global and detailed routers adjust the signal routes to insert the via pillars. IC Compiler II provides low skew, high-performance clock designs with highly customizable mesh and automatic H-tree creation for clocks. IC Compiler II also provides automated bus routing to match resistance and capacitance on critical nets. It supports non-default routing and user-specified layer width and spacing.
"Synopsys' expertise in delivering an integrated flow from front-end to physical implementation, combined with TSMC's leadership in process technology, makes delivery of innovations that enable high-performance designs possible", stated Bijan Kiani, vice president of product marketing for the Design Group at Synopsys. "These innovations will enable our mutual customers to build some of the most advanced, high-performance designs today."
"We want to ensure that semiconductor designers are able to build the fastest chips using the latest process technology to meet the high-performance needs of modern SoCs", stated Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "In the current design flow, full custom or semi-custom flows and methodology are used to achieve higher speed. Through our collaboration with Synopsys, we are enabling a new ASIC-based design flow and methodology for our High Performance Compute Platform."