Primeur Magazine:So, you design a chip and pass it over to a factory or manufacturer and then you get a real chip back?
John Shalf:You can indeed. The way that we work on it for the purpose of conducting research, is that you can get the entire chip design to build on an FPGA platform, which is slower than a real chip would be but is as accurate. You can also run it through the entire process of rodding the wires and gates for the chip to get estimates of how much power and area the chip would take if you produced it. Certainly, if you have a chip design that is performant and meets your power and area, you can, with some additional cost, tape it out at a foundry like TSMC. This has overcome some of the impediments for academic researchers and laboratory researchers experimenting in this area because we don't have the high IP costs.
Primeur Magazine:You mentioned some example of students who were designing a chip which was fast and very good already. Is this something like how the future will look like, that you can design your own chips?
John Shalf:We are coming near the end of Moore's Law as we know it. We have been able to benefit from having pretty much the same design for a period of time, increased the clock frequency, made the pipelines deeper but it was still practically the same. After that gave out, we went with multi-core which means having copies of the same core over and over, but by 2025 - and it is already happening today - performance improvements are tapering off. We no longer are able to get improvement by shrinking things. This means we need to specialize. Specialization has not been taking off in the past because it is very expensive to design verified new hardware. Unless the industry finds a way to work with academia possibly to reduce the cost of specialization, the industry will be in trouble. I believe in the future. The kind of tools that we are talking about here that we are using to create these open source hardware designs will ultimately also bring down the costs of designing more custom-tailored chips so that we can continue to see performance increases in the absence of increases from technology scaling.
Primeur Magazine:The new number one in the TOP500 - the Sunway TaihuLight - has specially designed processors - more or less - for a supercomputer. How does that compare or is it something different?
John Shalf:There is word of what I heard from my other colleagues in China that they were originally digital signal processing (DSP) cores. They combined an array of 64 of them into a processor array. This is similar to what I have been describing in my workshop talk. We have a Network-on-Chip fabric that connects a bunch of very simple cores together as your key processing element. Then they took four of those chips and combined them together in a wafer. If you think of the building block as an embedded DSP core, it is in fact extremely similar to what we are talking about here, except that the core designs we are working with are open.
Primeur Magazine:Which things are you working on currently? What will we see in the next years?
John Shalf:We have this very simple, hastily put together, demonstration for Supercomputing. We demonstrated a 96-core SoC running on an FPGA system with Hybrid Memory Cube and very simple RISC-V Z-Scale cores. The Z-Scales lack floating point. We also had a very rudimentary software environment. By next year, we are going to move to the RISC-V Rocket cores which are dual-issue, full floating point, 64-bit cores and keep the Hybrid Memory Cubic force and be able to demonstrate UPC++ or PGAS codes running natively on the hardware platform. We very much like to tape this out, as we would have a real chip but with the budget that we have, we do most of our work with the FPGAs to demonstrate the concept.
Primeur Magazine:It would be nice to see the results next year at this conference.