Josh Fryman looked at the evolution of electronics, how we moved from mechanical to electro-mechanical, and then to vacuum tubes, bipolars, NMOS and CMOS. Now we ask ourselves what is coming next. All cross-road technologies show three basic components: gain, signal/noise and scalability in some shape or form. However, scalability is an overused term. What does it mean exactly? There are three dimensions: performance, energy and price/performance, Josh Fryman explained. We can look at these dimensions as a form of tenets. There is a signal coming in and the engineer is adding some energy to it to gain on the signal and do something with it on the other side. The second is signal/noise isolation. The engineer has to make sure to amplify the signal to control the noise that he cannot eliminate. The engineer as a third component has to have scalability in some measure by physical shrinking or adding force. These are the three fundamentals to actually have a viable technology.
There is an extra tenet, called the Shalf's tenet, which represents high volume manufacturability. If it is not possible to manufacture it at scale, the engineer cannot use the technology. The engineer needs to drive the ecosystem to keep making forward progress.
Next, Josh Fryman talked about scaling and electro-mechanical relays. In 1928, the Otis elevator was developed. If we look at this large physical construct and we see what we are having to day, this is the effect of scaling over 70 years. One can also look at vacuum tubes in the twenties, thirties, fifties and sixties of the past century, there is a continuous scaling of the technology. On the semiconductor front, the first transistor ultimately led to integrated circuit from which the Intel processors were developed. The engineer has in cubic meters what he is doing with a technology to achieve something. This represents a nice curve in terms of scaling. In terms of energy, there is a little trouble at the end: the engineer does not quite get what he wants. The cost is continuously regressing.
Josh Fryman asked himself what is in sight after CMOS. Which technology shows gain? What is there to be done to have a satisfactory signal to noise ratio at room temperature? Josh Fryman insisted on having real factors. The industry classically was very bad about performing full power with things like the laser and the power numbers. We also have to worry about scalability, performance costs and energy, all these things factor in. That is why research has to continue in order to find a viable technology. Once it is found, it will take 10 to 15 years to mature. Until then, we have no other choice than having CMOS to continue. This is not because it is necessarily the best technology but there is still no alternative.
There are three ways to look at this, according to Josh Fryman. The first one is to remove waste and reclaim efficiency. The second one is to employ known techniques. They have been documented for years. The third one is to look at multi-disciplinary solutions. To illustrate the reclaiming of the waste from µArchitecture, Josh Fryman showed a slide that had on-die cache, pipelined; super-scalar; out of order specutative; deep pipeline; and back to non-deep pipeline on the X-as. The trend line shows that until you get down to the reduction of the core architecture, you are gaining on efficiency using simplicity. The big win is energy efficiency. By choosing directly to simplify the design, to roll back the clock, energy-efficiency shoots way back up.
We can use plenty of techniques because they are known to us and we know how to use them, Josh Fryman stated. He gave an example about chasing tunnel FETs. The idea is to look at the drain current versus the gate voltage. The CMOS sub-threshold slope is 60 megavolt per decade. What is shown is the leakage variant. Tunnel FETs are providing a much deeper curve. Their leakage is fantastic compared to classic transistors. The drawback is that you have is the big gap in the amount of current that flows. Tunnel FETs perform brilliantly as long as they don't push back at 100 MegaHertz. The engineer can tweak the materials involved to get the performance back up while the curve looks exactly like a regular transistor. Why does he perform this exercise? Because he has transistors, Josh Fryman explained.
The engineers do get benefits from things like tunnel FETs but they have to go back and look at what they are trying to do with the technology. Are they using the wrong tool for the wrong job? With a steep subthreshold slope, there is lower leakage power. With lower ON current, there is lower performance. This meets the first three tenets but in research only. It is not mature enough for the fourth tenet.
When we look at near threshold voltage operation and examine the frequency versus the voltage. At maximum voltage, the frequency is nice but once as the engineer starts to bring the voltage down the frequency is corresponding false. Looking at the power that is consumed at this stage of the operation, the energy-efficiency of the operation becomes important. As the engineer pulls the voltage down and even though the frequency drops, the energy-efficiency is doing well. The engineer can exploit this since he doesn't need tunnel FETs to get energy-efficiency, even if he has to pay for it in some form, such as frequency or turning more cores to get the same pattern of performance.
The engineers built an experimental NTV processor in 2012 with a wide dynamic range. The energy-efficiency is very high in NTV and not so good when you are at the high end high power range. You have to decide what you are trying to raise to get a job done in a certain amount of time: cranking up the voltage or if you have lots of time, you can bring the voltage down. Josh Fryman showed how low the frequency is when doing NTV. The energy-efficiency may be nice but what about the cost?
Josh Fryman also showed the technique of fine-grain power management where the energy-efficiency increases by 60%. In 2006-2007, the engineers were demonstrating different ways to design the chip and the use of agressive power controls. There are 21 dynamic sleep regions in the actual type. The engineers let the system turn dies on and off the sleep state which provides significant energy savings.
To illustrate the multi-disciplinary approach, Josh Fryman gave an example of resiliency for asymptotic TMR. When you detect an error in the hardware, you can have a correction in the software. The software is reactive and the hardware is proactive. The proactive side is about planning ahead for the future. The engineer is going to design the system, the software and the hardware to periodically check itself. In case of a failure condition, should the voltage be brought up, has work to be migrated from something? The strategy depends on mean time to fault. If time is really large, traditional check-pointing may be good enough but if time is really short, we need a new technology, Josh Fryman explained.
From a user experience, you have the classic software layer at run time sitting on top of the hardware and you have the reactive and predictive side to this. How does this interact with the entire stack. You have user codes, run times and programming support tools. All these things need to be made aware of the underlying assumptions of the system.
To conclude Josh Fryman said there is nothing in sight today to replace CMOS. CMOS must continue until then. There is a need to reclaim the efficiency. To do this, we have to be brave and start thinking out of the box and go back to those known techniques. The future is bright but we need to get our heads out of the sand and make complex things more simple.
The workshop is covered in full in five articles: