Dr. Renduchintala said Intel has redefined its product innovation model for the data-centric era of computing, which "requires workload-optimized platforms and effortless customer and developer innovation". He shared expected performance gains resulting from a combination of technical innovations across six pillars - process and packaging, architecture, memory, interconnect, security and software - giving insight into the design and engineering model steering the company's product development.
"While process and CPU leadership remain fundamentally important, an extraordinary rate of innovation is required across a combination of foundational building blocks that also include architecture, memory, interconnect, security and software, to take full advantage of the opportunities created by the explosion of data", Dr. Renduchintala stated. "Only Intel has the R&D, talent, world-class portfolio of technologies and intellectual property to deliver leadership products across the breadth of architectures and workloads required to meet the demands of the expanding data-centric market."
Intel's first volume 10nm processor, a mobile PC platform code-named "Ice Lake", will begin shipping in June. The Ice Lake platform will take full advantage of 10nm along with architecture innovations. It is expected to deliver approximately 3 times faster wireless speeds, 2 times faster video transcode speeds, 2 times faster graphics performance, and 2.5 to 3 times faster artificial intelligence (AI) performance over previous generation products1. As announced, Ice Lake-based devices from Intel OEM partners will be on shelves for the 2019 holiday season. Intel also plans to launch multiple 10nm products across the portfolio through 2019 and 2020, including additional CPUs for client and server, the Intel Agilex family of FPGAs, the Intel Nervana NNP-I (AI inference processor), a general-purpose GPU and the "Snow Ridge" 5G-ready network system-on-chip (SOC).
Building on a model proven with 14nm that included optimizations in 14+ nm and 14++ nm, the company will drive sustained process advancement between nodes and within a node, continuing to lead the scaling of process technology according to Moore's Law. The company plans to effectively deliver performance and scaling at the beginning of a node, plus another performance improvement within the node through multiple intra-node optimizations within the technology generation.
Dr. Renduchintala provided first updates on Intel's 7nm process technology that will deliver 2 times scaling and is expected to provide approximately 20 percent increase in performance per watt with a 4 times reduction in design rule complexity. It will mark the company's first commercial use of extreme ultraviolet (EUV) lithography, a technology that will help drive scaling for multiple node generations.
The lead 7nm product is expected to be an Intel Xe architecture-based, general-purpose GPU for data centre AI and high-performance computing. It will embody a heterogeneous approach to product construction using advanced packaging technology. On the heels of Intel's first discrete GPU coming in 2020, the 7nm general purpose GPU is expected to launch in 2021.
Dr. Renduchintala previewed new chip designs that leverage advanced 2D and 3D packaging technology to integrate multiple intellectual property (IP), each on its own optimized process technology, into a single package. The heterogeneous approach allows new process technologies to be leveraged earlier by interconnecting multiple smaller chiplets, and larger platforms to be built with unprecedented levels of performance when compared to non-monolithic alternatives.
Dr. Renduchintala unveiled the performance gains that resulted from innovative development of the client platform code-named "Lakefield". The approach is symbolic of the strategic shift in the company's design and engineering model that underpins Intel's future product roadmaps. To meet customer specifications, a breadth of technical innovations including a hybrid CPU architecture and Foveros 3D packaging technology were used to meet always-on, always-connected and form-factor requirements while simultaneously delivering to power and performance targets. Lakefield is projected to deliver approximately 10 times SOC standby power improvement and 1.5 to 2 times active SOC power improvement relative to 14nm predecessors, 2 times graphics performance increases, and 2 times reduction in printed-circuit-board (PCB) area, enabling OEMs to have more flexibility for thin and light form factor designs.