IBM scientists envision standalone PCM as well as hybrid applications, which combine PCM and flash storage together, with PCM as an extremely fast cache. For example, a mobile phone's operating system could be stored in PCM, enabling the phone to launch in a few seconds. In the enterprise space, entire databases could be stored in PCM for blazing fast query processing for time-critical online applications, such as financial transactions.
Machine learning algorithms using large datasets will also see a speed boost by reducing the latency overhead when reading the data between iterations.
PCM materials exhibit two stable states, the amorphous (without a clearly defined structure) and crystalline (with structure) phases, of low and high electrical conductivity, respectively.
To store a '0' or a '1', known as bits, on a PCM cell, a high or medium electrical current is applied to the material. A '0' can be programmed to be written in the amorphous phase or a '1' in the crystalline phase, or vice versa. Then to read the bit back, a low voltage is applied. This is how re-writable Blue-ray Discs store videos.
Previously scientists at IBM and other institutes have successfully demonstrated the ability to store 1 bit per cell in PCM, but at the IEEE International Memory Workshop in Paris, May 16-18, 2016, IBM scientists are presenting, for the first time, successfully storing 3 bits per cell in a 64k-cell array at elevated temperatures and after 1 million endurance cycles.
"Phase change memory is the first instantiation of a universal memory with properties of both DRAM and flash, thus answering one of the grand challenges of our industry", stated Dr. Haris Pozidis, an author of the paper titled "Demonstration of Reliable Triple-Level-Cell (TLC) Phase-Change Memory" and the manager of non-volatile memory research at IBM Research - Zurich. "Reaching 3 bits per cell is a significant milestone because at this density the cost of PCM will be significantly less than DRAM and closer to flash." The other authors are M. Stanisavljevic, A. Athmanathan, N. Papandreou, T. Mittelholzer, and E. Eleftheriou.
To achieve multi-bit storage IBM scientists have developed two innovative enabling technologies: a set of drift-immune cell-state metrics and drift-tolerant coding and detection schemes.
More specifically, the new cell-state metrics measure a physical property of the PCM cell that remains stable over time, and are thus insensitive to drift, which affects the stability of the cell's electrical conductivity with time. To provide additional robustness of the stored data in a cell over ambient temperature fluctuations a novel coding and detection scheme is employed. This scheme adaptively modifies the level thresholds that are used to detect the cell's stored data so that they follow variations due to temperature change. As a result, the cell state can be read reliably over long time periods after the memory is programmed, thus offering non-volatility.
"Combined these advancements address the key challenges of multi-bit PCM, including drift, variability, temperature sensitivity and endurance cycling", stated Dr. Evangelos Eleftheriou, IBM Fellow.
The experimental multi-bit PCM chip used by IBM scientists is connected to a standard integrated circuit board. The chip consists of a 2 × 2 Mcell array with a 4- bank interleaved architecture. The memory array size is 2 × 1000 µm × 800 µm. The PCM cells are based on doped-chalcogenide alloy and were integrated into the prototype chip serving as a characterization vehicle in 90 nm CMOS baseline technology.
At the 2016 OpenPOWER Summit in San Jose, California, IBM scientists demonstrated, for the first time, phase-change memory attached to POWER8-based servers, made by IBM and TYAN Computer Corp., via the Coherent Accelerator Processor Interface (CAPI) protocol. This technology leverages the low latency and small access granularity of PCM, the efficiency of the OpenPOWER architecture and the CAPI protocol. In the demonstration the scientists measured very low and consistent latency for 128-byte read/writes between the PCM chips and the POWER8 processor.
The paper titled "Multilevel-Cell Phase Change Memory: A Viable Technology" by Aravinthan Athmanathan, Milos Stanisavljevic, Nikolaos Papandreou, Haralampos Pozidis and Evangelos Eleftheriou, is available at DOI: 10.1109/JETCAS.2016.2528598 .