According to ARM, Advanced Driver Assistance Systems (ADAS) equipped vehicles will require at least 100x more compute performance by 2024 compared to 2016 models, with functional safety an industry priority. By offering the first-ever applications processor functional safety package for partners ARM is helping to enable this vision. Currently, companies must build complete safety cases on a chip-by-chip basis, duplicating effort and increasing industry costs. Greater supply chain efficiency is vital for vehicle makers who must balance increasing compute demands with next generation models but still deliver competitive pricing.
"Exciting new technologies are being deployed by manufacturers to make vehicle intelligence the prime consideration for consumers", stated Richard York, vice president of embedded marketing at ARM. "ADAS promises far greater intelligence and road safety, and the efficiency advantages of the ARM ecosystem mean our partners are well-positioned to deliver this technology. Today's announcement re-affirms our commitment to help shape future automotive markets."
The ARM Cortex-A safety documents package:
"With an 18 percent unit CAGR, ADAS features are exhibiting the highest growth within the automotive electronics domain as vehicle makers look to differentiate on enhanced product safety", stated Chris Webber, vice president of automotive at research firm Strategy Analytics. "These technologies are stepping stones on the road to fully autonomous driving systems which will demand robust functional safety integrated within the control architecture development. This must be coupled with processors capable of higher performance code execution and data throughput."
The path to high performance, automotive-grade, System on Chips (SoCs) will enable future ADAS based on radar and vision technology and other driver assist and infotainment capabilities.
Today, premium cars have more than 100 processors on board utilizing tens of millions of lines of code. To meet future ADAS demands, ARM expects processor performance compared to 2016 vehicles to increase 20x by 2018, 40-50x by 2020 and 100x by 2024. Meeting this ambition will require deeper functional safety support and higher performance, energy-efficient SoCs.
ARM's partners are using the latest technology to serve multiple automotive needs such as infotainment as well as ADAS. This includes the Cortex-A53 and Cortex-A57 processors, and ARM partners Freescale Semiconductor and Texas Instruments have now announced they will adopt ARM's recently launched Cortex-A72 processors for vehicle SoCs.
"ARM's Cortex-A72 processor technology delivers exceptional power and performance that aligns to Freescale's strategic vision of scalable solutions for our automotive customers", stated Ron Martino, vice president of applications processors and advanced technology adoption, MCU organisation at Freescale. "As the world's top carmakers and their suppliers develop infotainment systems with Freescale's future i.MX applications processors, the Cortex-A72 cores will play an important role in enabling next generation services and application performance."
"Today's consumers expect their driving experience to be fun with increased connectedness and telematics functionality for entertainment purposes, as well as a higher emphasis on ADAS applications to ensure a safe ride", stated Curt Moore, general manager of automotive processors at Texas Instruments. "As compute performance requirements in infotainment and ADAS applications continue to grow, ARM Cortex-A processors are critical building blocks enabling the next generation driver experience. We are pleased to continue to enable our customers to push the envelope of performance in the ADAS and Infotainment markets through our licensing of the newest ARM Cortex-A72 processor."
"With the move to ever increasing driver assistance and ever-more connected vehicles, safety systems and advanced driver interfaces, the compute power requirements of vehicles is set to significantly increase", stated Prof. Dr. Ralf Herrtwich, director of driver assistance and chassis systems at Daimler AG. "This is why ARM Cortex-A processors are increasingly being used for automotive applications. ARM extending its commitment and safety investment across its core portfolio, enables us to meet requirements of functional safety standards such as ISO 26262 for ADAS systems."
"Renesas has been offering ARM-based SoC technology to the Automotive Information System market for several generations and in multiple products", stated by Masahiro Suzuki, vice president and chief of automotive information system business division at Renesas Electronics Corporation. "We believe safety features that enable ADAS and automotive cockpit systems are becoming an essential element and functional safety is engrained in the nature of Renesas. We are expanding our strategic partnership with ARM to achieve a safer, more secure and comfortable driving environment powered by Renesas automotive products."
"Xilinx is already in full automotive OEM production and is a leader in enabling flexible and scalable ADAS camera systems with our 28nm Zynq-7000 SoCs with dual-core Cortex-A9", stated Nick DiFiore, director of the automotive segment at Xilinx. "As ADAS performance and functional safety requirements increase, Xilinx will remain on the leading edge with our Zynq UltraScale+ MPSoC architecture which integrates ARM Cortex-A53 cores, Cortex-R5 cores, and programmable logic on a single chip. ARMs announcement and investment in functional safety is very welcome as we work closely with our automotive customers at the silicon and system level to clear the hurdles associated with the ISO-26262 Automotive Safety Integrity Levels."
"We are seeing multiple inquiries with increasing emphasis and urgency on functional safety compliance and are happy to extend our offer of certified Software Test Libraries (fRSTL) to ARM Cortex-A processors", stated Silvano Motto, CEO of YOGITECH. "This will enable customers to combine the ARM Safety Package with YOGITECH SW Test Libraries to cover all aspects of ISO26262 standard from systematic to HW random failures."