The new Cadence digital full flow delivers the PPA and throughput benefits through the following key enhancements:
"The new digital full flow enhancements build upon the widely adopted integrated flow, further advancing Cadence's digital and sign-off design leadership position and enabling customers to achieve SoC design excellence", stated Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. "We've collaborated closely with our customers who are under pressure to meet compressed schedules with increasingly large designs, offering them the features they need to realize PPA gains more efficiently."
The Cadence digital full flow consists of the Innovus Implementation System, Genus Synthesis Solution, Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution. It provides customers with a fast path to design closure and better predictability and supports the company's Intelligent System Design strategy, which enables advanced-node system-on-chip (SoC) design excellence.
"We spend a significant effort tuning our high-performance cores to meet our aggressive performance goals. Using the new ML capabilities in the Innovus Implementation Systems GigaOpt Optimizer, we were able to automatically and quickly train a model of our CPU core, which resulted in an improved maximum frequency along with an 80% reduction in total negative slack. This enabled 2x shorter turnaround time for final sign-off design closure", stated Dr. SA Hwang, general manager of Computing and Artificial Intelligence Technology Group at MediaTek.
"The Cadence digital full flow with iSpatial technology accurately predicts full placement optimization of PPA and enabled us to achieve 3x faster design turnaround time by quickly iterating on RTL, constraints and floorplan while improving total power by 6%. Furthermore, Cadence's unique ML capabilities allowed us to train a model of our design on Samsung Foundry's 4nm EUV node, which helped us further achieve a 5% performance improvement and 5% leakage power savings", stated Jaehong Park, executive vice president of Foundry Design Platform Development at Samsung Electronics.