On Tuesday, June 18, John Shalf, from Lawrence Berkeley National Laboratory (LBNL) will offer his thoughts on how the slowdown and eventual demise of Moore's Law will affect the prospects for high performance computing (HPC) in the next decade. For the past 50 years, HPC and the IT industry overall has relied on Moore's observation that a doubling of performance roughly every two years would be predictably delivered by advances in semiconductor manufacturing. But as transistor dimensions have approached single digit nanometers (nm), the rate of progress has slowed. At three nanometers, these structures are expected to be less than a dozen silicon atom across, which will likely be the practical limit using known lithography techniques.
John Shalf, who heads up the Computer Science Group at LBNL, will talk about how this erosion of Moore's Law has impacted processor technology roadmaps and how it will affect the first exascale supercomputers scheduled to come online early in the next decade. He will also discuss how the flattening of lithography improvements will shape the successors to those initial machines.
Beside this role as the department head for the Computer Science Group at Berkeley lab, John Shalf was recently the deputy director of Hardware Technology for the Department of Energy's Exascale Computing Project. In his spare time, he coauthored over 80 publications in the field of parallel computing software and HPC technology, encompassing three best papers, including the widely cited report "The Landscape of Parallel Computing Research: A View from Berkeley". He also coauthored the 2008 "ExaScale Software Study: Software Challenges in Extreme Scale Systems", which established the Defense Advanced Research Project Agency's (DARPA) information technology research investment strategy.
John Shalf's Tuesday presentation will be followed on Wednesday, June 19, with the closing keynote by Prof. Dr. Thomas Sterling of Indiana University. Thomas Sterling, who directs the Continuum Computer Architecture Laboratory at the university, will present his annual retrospective of the most important developments in HPC over the last 12 months. As is his tradition, he will discuss all the major advances that have taken place over the past year, and the challenges that surround them. Thomas Sterling will also review the changing nature of HPC applications and how they are influencing hardware designs and user preferences.
His closing address this year promises to be more forward-looking than usual, reflecting the anticipation of the first exascale systems expected to be deployed in just two years. This performance milestone is being reached at a time when the scope of HPC is expanding to include elements of machine learning and the broader category of artificial intelligence. At the same time, recent advances in quantum and neuromorphic computing suggest that traditional HPC platforms will soon be challenged by non-von Neuman architectures. Thomas Sterling will weave all these elements into his keynote and provide his thoughts on the significance of these technologies to the field of high performance computing and its practitioners.
An icon in the supercomputing community, Thomas Sterling holds the position of Professor of Intelligent Systems Engineering at the Indiana University School of Informatics, Computing, and Engineering as well as serves as the PI of the Continuum Computing Architecture Project at the Department of Intelligence Systems Engineering. Thomas Sterling has engaged in applied research in parallel computing system structures, semantics, and operation in industry, government labs, and academia. Thomas Sterling is best known as the "father of Beowulf" for his pioneering research in commodity/Linux cluster computing for which he shared the Gordon Bell Prize in 1997.