DRAM operation is measured by presence (1) or absence (0) of charge. The geometry shrink poses a challenge in terms of the capacitive load to the connection point. How do we separate signal from noise? This takes time, according to Dean Klein.
We have the CPU versus memory access time. The issue in not speed but density. The speed has stayed virtually flat. The gap is called the Memory Wall.
Power is a problem as well. A DIMM is not so bright. All memory cells become active and there are 8K cells for each active page. The overfetch means that 8K bits are activated per die and there are 32 bits used per fetch which leads up to 256.
As far as exascale computing is concerned, Dean Klein gave an example for reliability and resiliency. The DRAM endurance is larger than 1E15. The systematic failures are not covered. The communication between CPU and memory is essentially "open loop". The address failures on the bus are undetectable as well as the command failure on the bus.
There are also issues with memory performance, referred to as the Memory Wall. Solutions for the memory problem consist in evolutionary standards such as DDR4. The DDR4 introduction is expected in 1H'2012 but it is not going to take us to exascale, Dean Klein feared. The bandwidth will be higher with a high density.
The Memory Wall already existed in the 90's. The evolutionary standards do not address the Memory Wall.
The Hybrid Memory Cube (HMC) is larger than 1000 TSV's. It is larger than 10x bandwidth of a DDR3 DIMM
fraction of the power and 4 to 8 times more dense.
The first generation of the HCM module is a technology demonstrator with 1Gb DRAM array; 512 MB total DRAM cube; 128GB/s bandwidth; and 10 pJ/bit energy. The technology is being demonstrated now.
HMC is a signal characterization platform. The HMC DRAM and system architecture promises increased performance, increased parallelism, reduced latency, and reduced power.
The world's first hard drive was developed in 1956 as the RAMAC with 5MB of capacity and 55 bits per inch.
HDD techniques for density improvement are shingle writing but unfortunately shingle writing is a problem for performance.
Dean Klein also mentioned the NAND opportunities. At 30 nm and beyond, we can count the electrons on the floating gate. At 20 nm the floating gate interference is about 50% of the cell capacitance making MC capability more difficult.
The 3D floating gate with PCM, Mox CT RAM, CBM, and STTRAM is going to take 6 to 8 years. The economic reality is getting tough as well. Scanners are an expensive technology.
Dean Klein concluded that the costs to achieve advanced processes continue to rise. Niche markets using older technologies become a refuge for many companies. The 3-4 DRAM companies will likely continue to make leading edge components. Rationalization of the industry will allow innovation.
The future CPU architecture will basically be the technology that is in a CD-Rom. How do we cool it, is the question. The smaller we get, the lower the power becomes.
There are however opportunities for innovation. Memory companies will exercise the third dimension and will give CPU's and GPU's opportunities to increase performance while reducing power. The memory abstraction wil allow better tuning of the solution, allowing DRAM and NVM's to coexist cleanly. NAND has a future in HPC, but other NVM's will offer attractive advantages and will be used as well.
Memory makers have solutions for exascale and a desire to help but do not control the infrastructure
What can you do about that, Dean Klein challenged the audience.