Luca Carloni started by saying that we are evolving from multi-core to many-core architectures. The growing trend in multi-core architectures is straining on- and off-chip electronic interconnects. The Networks-on-Chip allow to build carefully-engineered shared channels optimized for communications, with many advantages, including resource efficiency, design simplicity, IP reusability/assembly, high performance, programmability, and scalability but they do not resolve the issue of the power.
We are facing an off-chip communication bottleneck. The computation scales but the global communication does not keep up. On-chip bus-based schemes do not scale and the traditional off-chip I/O bottleneck problem is getting even worse.
Future systems will be I/O limited, predicted Luca Carloni. The I/O is limited by pin/pad and density/area.
But why should we start using silicon photoic Networks? Because they will change the rules for
bandwidth-per-Watt, stated Luca Carloni. The photonics modulate and receive a data stream once per communication event. The off-chip BW versus the on-chip BW works for nearly the same power. There is a
wavelength parallelism: the broadband switch entirely routes the multi-wavelength stream while electronics
buffer, receive and re-transmit the stream.
Why do we want silicon photonic networks now? There is a growing research area at Columbia, Cornell, MIT/UCB, Sun, HP/Wisconsin/Utah and some other locations in the United States. Luca Carloni described the new vision to create a hybrid photonic NoC as a subsystem of future 3D integrated circuits.
If we take a look at silicon photonics for exascale computing, we can distinguish a series of
photonic-network building blocks that are needed. The first one is a broadband waveguide. This basic Si-photonic medium has to carry ultrahigh-bandwidth WDM data streams and will face 3dB-1.5dB/cm of propagation loss.
As a second building block we have to consider fiber couplers and waveguid crossing. A horizontal coupling with inverse taper preserves the very large bandwidth of the waveguide with less than 1 dB insertion loss. The next step consists in a stable packaging of a ribon of many fibers with low insertion loss.
The third building block really constitutes a key building block, according to Luca Carloni. It is the micro-ring resonator for wavelengths that resonate within the ring. They are coupled from the waveguide and lost in the ring due to sidewall scattering. They are very versatile. Their property is FSR function of the diameter.
The fourth building block is the translator consisting of a cascade of micro-ring modulators.
The fifth building block ia a 2x2 switch for multi-wavelength switch with the following properties, including a mirror structure and a fast control of resonance through carrier injection. The next step is to decrease insertion loss.
The sixth building block consists of a higher-order (4x4) non-blocking switch and a bi-directional 4x4 non-blocking switch.
The photodetector converts light into an electric current and the main photoreceiver component. Important is the sensitivity of the receiver.
At Cornell one can find a first complete silicon photonic link with an integrated optical interconnect provided with a silicon electro-optical modulator.
The advantages of photonic technology are the bit rate transparency: the transmission/switching power is independent of the bandwidth. There is low loss for power independent of distance. The wavelength division multiplexing is guaranteeing a huge transmission. So photonics promise low loss, large bandwidth, and bit-rate, according to Luca Carloni.
The speaker also addressed hybrid photonic NoC. The computer-aided design of silicon photonic interconnection networks enable photonic devices to be fundamentally different than electronics. So new tools and methodologies are need for a photonic interconnection networks design exploration. It is necessary to link the device research to the network architecture design.
PhoenixSim is a CAD environment for the analysis and optimization of chip-scale photonic networks.
The last five years have seen major breakthroughs in the fabrication of all the devices necessary to build chip-scale interconnection networks, concluded Luca Carloni. We need a hybrid network-design approach. In order to build networks that overcome power and memory walls, it is necessary to combine the best of both worlds (electronic and photonic).
Luca Carloni stressed that it is an exciting interdisciplinary research to realize the promise of chip-scale phtonics communication. This research requires the support of vertically integrated research programmes combining networking and architectures.