NEXTGenIO publishes architecture that integrates a byte-addressable storage class memory (SCM) into standard compute cluster to increase I/O performance


NEXTGenIO node.
25 Jan 2018 Edinburgh - The NEXTGenIO project has published a deliverable "The NEXTGenIO Architecture" that outlines an architecture for a prototype HPC/HPDA system that integrates a byte-addressable storage class memory (SCM) into a standard compute cluster to provide greatly increased I/O performance for computational simulation and data analytics tasks.

The architecture both outlines the components and integration of the prototype system, and define a vision of what is required to integrate and exploit SCM to enable a generation of Exascale systems with sufficient I/O performance to ensure a wide range of workloads can be supported.

The hardware architecture, which is designed to scale up to an Exaflop/s system, uses high performance processors coupled with SCM in NVRAM (non-volatile random access memory) form, traditional DRAM memory, and an Omni-Path high performance network. It provides a set of compute nodes for HPC and HPDA tasks.

The system software will enable parallel I/O using the SCM technology, provide a multi-node filesystem for users to exploit, enable use of object storage techniques, and provide automatic check-pointing. These features, along with other systemware components, will enable the system to support traditional parallel applications with high efficiency, and newer computing models such as high performance data analytics.

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